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lt1768 1 the lt ? 1768 is designed to control single or multiple cold cathode fluorescent lamp (ccfl) displays. a unique mul- timode dimming scheme* combines both linear and pwm control functions to maximize lamp life, efficiency, and dimming range. accurate maximum and minimum lamp currents can be easily set. the lt1768 can detect and protect against lamp failures and overvoltage start-up conditions. it is designed to provide maximum flexibility with a minimum number of external components. the lt1768 is a current mode pwm controller with a 1.5a mosfet driver for high power applications. it contains a 350khz oscillator, 5v reference, and a current sense comparator with a 100mv threshold. it operates from an 8v to 24v input voltage. the lt1768 also has undervoltage lockout, thermal limit, and a shutdown pin that reduces supply current to 65 m a. it is available in a small 16-lead ssop package. n ultrawide multimode dimming tm range n multiple lamp capability n programmable pwm dimming range and frequency n precision maximum and minimum lamp currents maximize lamp lifetime n no lamp flicker under all supply and load conditions n open lamp detection and protection n 350khz switching frequency n 1.5a mosfet gate driver n 100mv current sense threshold n 5v reference voltage output n the 16-lead ssop package high power ccfl controller for wide dimming range and maximum lamp lifetime n desktop flat panel displays n multiple lamp displays n notebook lcd displays n point of sale terminal displays figure 1. 14w ccfl supply produces a 100:1 dimming ratio while maintaining minimum and maximum lamp current specifications 1768 ta01 c4 0.33 m f 250 1/4w r5* 0.025 q1 q1 l1 68 m h t1 33pf 33pf 0.1 m f c1 33 m f si3456dy mbrs130t3 lamp lamp r3 60.4k r1 49.9k r2 40.2k r4 16.2k c3 0.1 m f c4 10 m f c2 0.033 m f v in 8v ?24v prog 0v to 5v or 1khz pwm lt1768 di02 pgnd gate v c agnd c t prog di01 sense shdn r min r max pwm fault v ref v in 5v 2200pf 100 610 4 53 2 1 c4-wima mkp2 l1-coiltronics up4-680 t1-2 ctx110607 in parallel q1-zdt1048 *r5 can be metal pcb trace lamp current (ma) 0 10000 1000 100 10 1 0.1 8 1768 ta01b 2 4 6 10 dimming ratio (nits/nits) lamp output (nits) lamp manufacturers specified current range lamp output and dimming ratio vs lamp current applicatio s u features typical applicatio u descriptio u , ltc and lt are registered trademarks of linear technology corporation. multimode dimming is a trademark of linear technology corporation. *patent pending
lt1768 2 symbol parameter conditions min typ max units i q supply current 9v< v vin < 24v l 78 ma i shdn supply current in shutdown v shdn = 0v l 65 100 m a shdn pin pull-up current v shdn = 0v l 4712 m a shdn threshold voltage v shdn off to on l 0.6 1.26 1.8 v shdn threshold hysteresis l 100 200 300 mv v in undervoltage lockout v in off to on l 7.2 7.9 8.2 v v in undervoltage lockout v in on to off l 7.1 7.4 7.6 v v ref ref voltage i ref = C1ma l 4.9 5 5.1 v ref line regulation d v vin 8v to 24v i ref = C1ma l 720 mv ref load regulation d i ref C1ma to C10ma l 10 20 mv v rmax r max pin voltage l 1.225 1.25 1.275 v v rmin r min pin voltage l 1.22 1.26 1.30 v fsw switching frequency v prog = 0.75v, v sense = 0v l 300 350 410 khz maximum duty cycle v prog = 0.75v, v sense = 0v 93 % minimum on time v prog = 0.75v, v sense = 150mv 125 ns i prog prog pin input bias current v prog = 5v l 100 500 na v prog prog pin voltage for zero lamp current (note 2) l 0.45 0.5 0.55 v prog pin voltage for minimum lamp current (note 3) l 0.9 1 1.1 v prog pin voltage for maximum lamp current (note 4) l 3.8 4 4.2 v input voltage (v in pin) ............................................ 28v shdn pin voltage .................................................... 28v fault pin voltage ................................................... 28v prog pin voltage ................................................... 5.5v pwm pin voltage .................................................... 4.5v c t pin voltage ........................................................ 4.5v sense pin voltage .................................................... 1v dio1, dio2 input current ................................... 50ma r max pin source current ..................................... 750 m a r min pin source current ..................................... 750 m a v ref pin source current ....................................... 10ma operating junction temperature range lt1768c ................................................ 0 c to 125 c lt1768i ............................................ C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering 10 sec)................... 300 c order part number consult ltc marketing for parts specified with wider operating temperature ranges. absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics t jmax = 125 c, q ja = 100 c/w 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 pgnd di01 di02 sense vc agnd c t prog gate v in v ref fault shdn r min r max pwm lt1768cgn lt1768ign the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c, v vin = 12v, i dio1/2 = 250 m a, v prog = 0v, v pwm = 2.5v, i rmax = C100 m a, i rmin = C100 m a, unless otherwise specified. gn part marking 1768 1768i
lt1768 3 electrical characteristics symbol parameter conditions min typ max units i pwm pwm input bias current l 0.6 4 m a pwm duty cycle v prog = 1.75 45 50 55 % pwm frequency c t = 0.22 m f (note 7) 90 110 130 hz v dio1/2 dio1/2 positive voltage i dio = 14ma 1.7 1.9 v dio1/2 negative voltage i dio = C14ma C1.1 C1.3 v v vcclamp vc high clamp voltage v prog = 4.5v (note 8) 3.6 3.7 3.9 v vc switching threshold v prog = 4.5v (note 8) 0.5 0.7 0.95 v i sense sense input bias current v sense = 0v C25 C30 m a v sense sense threshold for current limit v vc = v vcclamp , duty cycle < 50%, v prog = 1v 85 100 115 mv v vc = v vcclamp , duty cycle 80%, v prog = 1v 90 mv i dio1/2 to i rmax ratio v prog = 4.5v (note 5) l 94 98 104 a/a v prog = 4.5v, i dio1 or i dio2 = 0, v vc = 2.5v, (note 5) 45 49 55 a/a i dio1/2 to i rmin ratio v prog < 0.75v (note 6) l 9 10 11 a/a v prog < 0.75v, i dio1 or i dio2 = 0, v vc = 2.5v, (note 6) 9 10 11 a/a i gate gate drive peak source current 1.5 a gate drive peak sink current 1.5 a gate drive saturation voltage v vin = 12v, i gate = C100ma, v prog = 4.5v l 9.8 10.2 v gate drive clamp voltage v vin = 24v, i gate = C10ma, v prog = 4.5v l 12.5 14 v gate drive low saturation voltage i gate = 100ma l 0.4 0.6 v open lamp threshold (note 9) 100 125 150 m a fault pin saturation voltage i fault = 1ma, i di01 , i di02 = 0 m a, v prog = 4.5v 0.2 0.3 v fault pin leakage current v fault = 5v 20 100 na thermal shutdowntemperature 160 c note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: this is the threshold voltage where the lamp current switches from zero current to minimum lamp current. for v prog less than the threshold voltage, lamp current will be at zero. for v prog greater than the threshold voltage, lamp current will be equal to the minimum lamp current. minimum lamp current is set by the value of the resistor from the r min pin to ground. see applications information for more details. note 3: this is the threshold voltage where the device starts to pulse width modulate the lamp current. for v prog less than the threshold voltage, lamp current will be equal to the minimum lamp current. for v prog greater than the threshold voltage, lamp current will be pulse width modulated between the minimum lamp current and some higher value. minimum lamp current is set by the value of the resistor from the r min pin to ground. the higher value lamp current is a function of the r max resistor to ground value, and the voltages on the pwm and prog pins. see applications information for more details. note 4: this is the threshold voltage where the lamp current reaches its maximum value. for v prog greater than the threshold voltage, there will be no increase in lamp current. for v prog less than the threshold voltage, lamp current will be at some lower value. maximum lamp current is set by the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c, v vin = 12v, i dio1/2 = 250 m a, v prog = 0v, v pwm = 2.5v, i rmax = C100 m a, i rmin = C100 m a, unless otherwise specified. the value of the resistor from the r max pin to ground. the lower value lamp current is a function of the r min and r max resistors, and the voltages on the pwm and prog pins. see applications information for more details. note 5: i dio1/2 to i rmax ratio is determined by setting i rmax to C100 m a, v prog to 4.5v, v vc to 2.5v, and then ramping a dc current out of the dio1/2 pins from zero until the dc current in the vc voltage source current equals zero. the i dio1/2 to i rmax ratio is then defined as (i dio1 + i dio2 )/i rmax . see applications information for more details. note 6: i dio1/2 to i rmin ratio is determined by setting i rmin to C100 m a, v prog to 0.75v, v vc to 2.5v, and then ramping a dc current out of the dio1/2 pins from zero until the dc current in the vc voltage source current equals zero. the i dio1/2 to i rmin ratio is then defined as (i dio1 + i dio2 )/i rmin . see applications information for more details. note 7: the pwm frequency is set by the equation pwmfreq = 22hz/ c t ( m f). note 8: for vc voltages less than the switching threshold, gate switching is disabled. note 9: an open lamp will be detected if either i dio1 or i dio2 is less than the threshold current for at least 1 full pwm cycle.
lt1768 4 typical perfor a ce characteristics uw temperature ( c) 5.10 5.08 5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 4.90 v ref voltage (v) 1768 g01 ?0 ?5 0 25 50 75 100 125 i ref = ?ma temperature ( c) 1.30 1.29 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 voltage (v) 1768 g02 ?0 ?5 0 25 50 75 100 125 v r min(v) v r max(v) i rmin = ?00 a i rmax = ?00 a temperature ( c) 80 76 72 68 64 60 56 52 48 44 40 shutdown current ( m a) 1768 g03 ?0 ?5 0 25 50 75 100 125 v shdn = 0v input voltage (v) 10 8 6 4 2 0 supply current (ma) 1768 g04 05 10 15 20 25 v rmin , v rmax vs temperature supply current in shutdown vs temperature supply current vs input voltage v ref vs temperature temperature ( c) 7.40 7.30 7.20 7.10 7.00 6.90 6.80 6.70 6.60 6.50 6.40 supply current (ma) 1768 g05 ?0 ?5 0 25 50 75 100 125 input voltage (v) 100 80 60 40 20 0 shutdown current ( m a) 1768 g06 05 10 15 20 25 v shdn = 0v temperature ( c) 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0 shutdown voltage (v) 1768 g08 ?0 ?5 0 25 50 75 100 125 v shdn on to off v shdn off to on supply current vs temperature supply current in shutdown vs input voltage undervoltage lockout threshold vs temperature shdn pull-up current vs input voltage shutdown threshold voltage vs temperature temperature ( c) 8.20 8.10 8.00 7.90 7.80 7.70 7.60 7.50 7.40 7.30 7.20 undervoltage lockout (v) 1768 g09 ?0 ?5 0 25 50 75 100 125 v uvl on to off v uvl off to on input voltage (v) 0 shdn pull-up current ( m a) 10 8 6 4 2 0 20 1768 g07 5 10 15 25 v shdn = 0v
lt1768 5 typical perfor a ce characteristics uw switching frequency vs temperature temperature ( c) 400 390 380 370 360 350 340 330 320 310 300 switching frequency (khz) 1768 g10 ?0 ?5 0 25 50 75 100 125 temperature ( c) 124 120 116 112 108 104 100 96 92 88 84 pwm frequency (hz) 1768 g11 ?0 ?5 0 25 50 75 100 125 c t = 0.22 f v pwm = 2.5v temperature ( c) 0.250 0.225 0.200 0.175 0.150 0.125 0.100 0.75 0.50 0.25 0 fault voltage (v) 1768 g12 ?0 ?5 0 25 50 75 100 125 i dio1 = 0 a i dio2 = 0 a i fault = 1ma i fault (ma) 0 450 400 350 300 250 200 150 100 1.5 2.5 1768 g13 0.5 1.0 2.0 3.0 3.5 fault voltage (mv) i dio1 = 0 a i dio2 = 0 a temperature ( c) 50 45 40 35 30 25 20 15 10 5 0 sense current ( m a) 1768 g14 ?0 ?5 0 25 50 75 100 125 v sense = 0v temperature ( c) 15.00 14.50 14.00 13.50 13.00 12.50 12.00 11.50 11.00 10.50 10.00 gate clamp voltage (v) 1768 g15 ?0 ?5 0 25 50 75 100 125 i gate = ?0ma v in = 24v v in = 12v fault pin saturation voltage vs current maximum gate voltage vs temperature sense pin bias current vs temperature pwm frequency vs temperature fault pin saturation voltage vs temperature dio current (ma) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 dio voltage (v) 1768 g24 2468 10 12 14 16 18 20 0 v c current ( m a) 3.75 3.74 3.73 3.72 3.71 3.70 3.69 3.68 3.67 3.66 3.65 v c clamp voltage (v) 1768 g25 0 50 100 150 200 250 300 350 400 450 500 vc clamp voltage vs current dio pin voltage vs current dio current (ma) 2.0 ?.8 ?.6 ?.4 ?.2 ?.0 ?.8 0.6 0.4 0.2 0 dio voltage (v) 1768 g20 ? ? ? ? ?0 ?2 ?4 ?6 ?8 ?0 0 dio pin voltage vs current
lt1768 6 typical perfor a ce characteristics uw temperature ( c) 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 v c clamp (v) 1768 g26 ?0 ?5 0 25 50 75 100 125 i vc = 500 m a temperature ( c) 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 v c switch threshold voltage (v) 1768 g27 ?0 ?5 0 25 50 75 100 125 pwm voltage (v) 0 pwm input current ( m a) 25 20 15 10 5 0 4 1768 g28 1 2 3 5 temperature ( c) 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 pwm input current ( m a) 1768 g29 ?0 ?5 0 25 50 75 100 125 v pwm = 2.5v temperature ( c) 200 180 160 140 120 100 80 60 40 20 0 bulb fault current threshold ( m a) 1768 g31 ?0 ?5 0 25 50 75 100 125 gate duty cycle (%) 120 110 100 90 80 70 60 50 40 30 20 sense threshold (mv) 1768 g32 0 102030 40 50 60 70 80 90 100 lamp fault current threshold vs temperature maximum sense threshold vs gate drive duty cycle pwm pin input current vs temperature vc switching threshold vs temperature pwm pin input current vs voltage vc clamp voltage vs temperature i rmax ( a) 110 108 106 104 102 100 98 96 94 92 90 i di01/2 to i rmax ratio (a/a) 1768 g33 0 ?0 ?20 ?80 ?40 ?00 v prog = 4.5v v vc = 2.5v i rmin ( a) 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 9.0 i di01/2 to i rmin ratio (a/a) 1768 g35 0 ?0 ?20 ?80 ?40 ?00 v prog = 0.75v v vc = 2.5v i dio1/2 to i rmax ratio vs r max current i dio1/2 to i rmax ratio vs r max current with a lamp fault i dio1/2 to i rmin ratio vs r min current i rmax ( a) 60 58 56 54 52 50 48 46 44 42 40 i di01/2 to i rmax ratio (a/a) 1768 g34 0 ?0 ?20 ?80 ?40 ?00 v prog = 4.5v v vc = 2.5v i di01 or i di02 = 0 a
lt1768 7 provides lamp current averaging and single pole loop compensation. agnd (pin 6): the agnd pin is the low current analog ground. it is the negative sense terminal for the internal reference and current sense amplifier. connect critical external components that terminate to ground directly to this pin for best performance. c t (pin 7): the value of capacitance on the c t pin deter- mines the pwm modulation frequency. the transfer func- tion of capacitance to frequency equals 22hz/c t ( m f). the frequency present on the c t pin also determines the maximum time allowed for lamp fault conditions. if the current in either dio1 or dio2 is less than 125 m a for a minimum of 1 pwm period, the fault pin is activated and the maximum allowable lamp current is reduced by ap- proximately 50%. if the current in both dio1 and dio2 is absent for a minimum of 1 pwm period, and the vc pin is clamped at 3.7v, the fault pin is activated and the gate drive of the part is internally latched off. the latch can be cleared by setting the prog voltage to zero or placing the lt1768 in shutdown mode. prog (pin 8): the prog pin controls the lamp current by converting a dc input voltage range of 0v to 5v to source current into the vc pin. the transfer function from pro- gramming voltage to vc current is illustrated in the follow- ing table. prog (v) vc source current ( m a) v prog < 0.5 0 0.5 < v prog < 1.0 i rmin 1.0 < v prog < v pwm pwm mode* v ct > v prog i rmin v ct < v prog 5 ? i rmax ? ( v pwm C 1v)/ 3v v prog > 4.0 5 ? i rmax *pwm duty cycle = [1 C (v pwm C v prog )/(v pwm C 1v)] ? 100% pwm (pin 9): the pwm pin controls the percentage of the prog range between 1v and 4v that is to be pulse width modulated. the percentage is defined by [(v pwm -1)/ 3] ? 100%. the minimum and maximum percentages are 25% (1.75v) and 100% (4v) respectively. taking the pwm pin above the 4v maximum will cause significant pwm input current to flow. (see pwm input current vs voltage curve in typical performance characteristics). pi n fu n ctio n s uuu pgnd (pin 1): the pgnd pin is the high current ground path. high switching current transients and lamp current flow through the pgnd pin. dio1/dio2 (pins 3/2): each dio pin is the common connection between the cathode and anode of two internal diodes. the remaining terminals of the diodes are con- nected to pgnd. in a typical application, the dio1/2 pins are connected to the low voltage side of the lamps. bidirectional lamp current flows into the dio1/2 pins and their diodes conduct alternately on the half cycles. the diode that conducts on the negative cycle has a percentage of its current diverted into the vc pin. this current nulls against the programming current specified by the prog and pwm pins. a single capacitor on the vc pin provides both stable loop compensation and an averaging function to the half wave-rectified lamp current. the diode that conducts on the positive cycle is used to detect open lamp conditions. if the current in either of the dio pins on the positive cycle is less than 125 m a for a minimum of 1 pwm cycle, then the fault pin will be activated and the maxi- mum source current into the vc pin will be reduced by approximately 50%. if the current in both of the dio pins on the positive cycle is less than 125 m a, and the vc pin hits its clamp value (indicating either an open lamp or lamp lowside short to ground fault condition) for a minimum of 1 pwm cycle, the gate drive will be latched off. the latch can be cleared by setting the prog voltage to zero or placing the lt1768 in shutdown mode. sense (pin 4): the sense pin is the input to the current sense comparator. the threshold of the comparator is a function of the voltage on the vc pin and the switch duty cycle. the maximum threshold is set at 100mv for duty cycle less than 50% which corresponds to approximately 3.7v on the vc pin. the sense pin has a bias current of 25 m a, which flows out of the pin. vc (pin 5): the vc pin is the summing junction for the programming current and the half wave rectified lamp current and is also an input to the current sense compara- tor . a fraction of the voltage on the vc pin is compared to the voltage on the sense pin (switch current) for switch turnoff. during normal operation the vc pin sits between 0.7v (zero switch current) and 3.7v (maximum switch current). a single capacitor between vc and agnd
lt1768 8 pi n fu n ctio n s uuu r max (pin 10): the r max pin outputs a regulated voltage of 1.25v that is to be loaded with an external resistor. the current through the external resistor sets the maximum lamp current. maximum lamp current in a dual lamp application will be approximately equal to 100 times i rmax when the voltage on the prog pin is greater than 4v. the value of r rmax must be greater than 5k and less than [r rmin ? 2.5 ? (v pwmC1 /3)] for proper pwm operation. r min (pin 11): the r min pin outputs a regulated voltage of 1.26v that is to be loaded with an external resistor. the current through the external resistor sets the minimum lamp current. minimum lamp current in a dual lamp application will be approximately 10 times the value of i rmin when the voltage on the prog pin is between 0.5v and 1v. to set the minimum current to zero (i rmin = 0 m a) for maximum dimming range, connect the r min pin to the v reg pin. the value of r rmin (r rmin = when r min is connected to v reg ) must be greater than the value of r rmax /[0.4 ? (v pwmC1 )/3] for proper pwm operation. shdn (pin 12): the shdn pin controls the operation of the lt1768. pulling the shdn pin above 1.26v or leaving the pin open will result in normal operation of the lt1768. pulling the shdn pin below 1v causes a complete shut- down of the lt1768 which results in a typical quiescent current of 65 m a. the shdn pin has an internal 7 m a pull-up source to v in and 200mv of voltage hysteresis. fault (pin 13): the fault pin is an open collector output with a sink capability of 1ma that is activated when lamp current falls below 125 m a in either dio1 or dio2 for at least 1 full pwm cycle. v ref (pin 14): the v ref pin is a regulated 5v output that is derived from the v in pin. the regulated voltage provides up to 10ma of current to power external circuitry. during undervoltage lockout, shutdown mode or thermal shutdown, drive to the v ref pin will be disabled. v in (pin 15): the v in pin is the voltage supply pin for the lt1768. for normal operation, the v in pin must be above an undervoltage lockout of 7.9v and below a maximum of 24v. gate (pin 16): the gate pin is the output of a npn high current output stage used to drive the gate of an external mosfet. it has a dynamic source and sink capability of 1.5a. during normal operation, the gate pin is driven high at the beginning of each oscillator period and then low when the appropriate current in the switch is reached. the gate pin has a minimum on time of 125ns and a maximum duty cycle of 93% at a frequency of 350khz. for input voltages less than 13v the gate will be driven to within 2v of v in . for input voltages greater than 13v the gate pin high level will be clamped at a typical voltage of 12.5v.
lt1768 9 block diagra w figure 2. lt1768 block diagram introduction the current trend in desktop monitor design is to migrate the lcd (liquid crystal display) technology used in laptops and instruments to the popular desktop display sizes. as lcd size increases uniform backlighting requires mul- tiple high power lamps. in addition, the lamps must have a dimming range and lifetime expectancy comparable to previous generations of desktop displays. cold cathode fluorescent lamps (ccfls) provide the highest available efficiency for backlighting lcd displays. the ccfl re- quires a high voltage supply for operation. typically, over 1000 volts is required to initiate ccfl operation, with sustaining voltages from 200v to 800v. a ccfl can operate from dc, but migration effects damage the ccfl and shorten its lifetime. to achieve maximum life ccfl drive should be sinusoidal, contain zero dc component, and not exceed the ccfl manufacturers minimum and maximum operating current ratings. low crest factor applicatio n s i n for m atio n wu u u sinusoidal ccfl drive also maximizes current to light conversion, reduces display flicker, and minimizes emi and rf emissions. the lt1768 high power ccfl control- ler, with its multimode dimming, provides the necessary lamp drive to enable a wide dimming range while main- taining lamp lifetime in multiple lamp ccfl applications. basic operation referring to the circuit in figure 1, ccfl current is con- trolled by a dc voltage on the prog pin of the lt1768. the dc voltage on the prog pin feeds the lt1768s multimode dimming block and is converted to source current into the vc pin. as the vc pin voltage rises, the lt1768s gate pin is pulse width modulated at 350khz. the gate pulse width is determined on a cycle by cycle basis by the voltage on the sense pin (l1s current multiplied by sense resistor r5) exceeding a predetermined voltage set by the vc pin. i rmax i rmin 0 1v 4v 1.25v 1.26v slope osc 1v v pwm pwm v c v ref r min r max v in c t fault shdn prog agnd di01 dio2 gate sense pgnd 12 14 15 10 11 9 8 7 6 5 3 2 16 13 4 1 control mode i vc v cclamp fault multi-mode dimming block pwm period undervoltage lockout thermal shutdown v ref (i dio1 + i dio2 ) gain i vc i dio2 < 125 a i dio1 < 125 a sw blank v in gate s q r 1768 bd
lt1768 10 applicatio n s i n for m atio n wu u u the current mode pulse width modulation produces an average current in inductor l1 proportional to the vc voltage. inductor l1 then acts as a switched mode current source for a current driven royer class converter with efficiencies as high as 90%. t1, c4 and q1 comprise the royer class converter which provides the ccfls with a zero dc, 60khz sinusoidal waveform whose amplitude is based on the average current in l1. sinusoidal current from both ccfls is then returned to the lt1768 through the dio1/2 pins. a fraction of the ccfl current from the negative half of its sine wave pulls against the internal current source at the vc pin closing the loop. a single capacitor on the vc pin provides loop compensation and ccfl current averaging, which results in constant ccfl current. varying the value of the internal current source via the multimode dimming block varies the ccfl current and resultant ccfl light intensity. multimode dimming previous backlighting solutions have used a traditional error amplifier in the control loop to regulate lamp current. the approach converted ac current into a dc voltage for the input of the error amplifier. this approach used several time constants in order to provide stable loop compensa- tion. this compensation scheme meant that the loop had to be fairly slow and that the output overshoot with start- up or load conditions had to be carefully evaluated in terms of transformer stress and breakdown voltage require- ments. in addition, intensity control schemes were limited to linear or pwm control. linear intensity control schemes provide the highest efficiency backlight circuits but either limit dimming range, or violate lamp minimum or maxi- mum ccfl current specifications to achieve wide dim- ming ratios. pwm control schemes offer wide dimming range but produce waveforms that may degrade ccfl life, and waste power at higher ccfl currents. the lt1768s multimode dimming eliminates the error amplifier con- cept entirely and combines the best of both control schemes to extend ccfl life while providing the widest possible dimming range. the error amplifier is eliminated by summing the current out of the multimode dimming block with a fraction of feedback lamp current to form the control loop. this topology reduces the number of time constants in the control loop by combining the error signal conversion scheme and frequency compensation into a single capaci- tor (vc pin). the control loop thus exhibits the response of a single pole system, allows for faster loop transient response and minimizes overshoot under start-up or overload conditions. referring to figure 2, the source current into the vc pin from the multimode dimming block (and resultant ccfl current) has five distinct modes of operation. which mode is in use is determined by the voltages on the prog and pwm pins, and the currents that flow out of the r max and r min pins. off mode (v prog < 0.5v), sets the vc source current to zero, actively pulls vc to ground, and inhibits the gate pin from switching which results in zero lamp current. minimum current mode (0.5v < v prog < 1v) sets the vc source current equal to the current out of the 1.26v referenced r min pin. the minimum vc source current determines the dimming range of the display. setting r rmin to produce the manufacturers minimum specified ccfl current guarantees the maximum ccfl lifetime for all prog voltages, but limits the dimming range. setting r rmin to produce currents less than the manufacturers minimum specified ccfl current increases dimming range, but places restrictions on the prog voltage for normal operation in order to maximize lifetime. to achieve the maximum dimming ratio possible, i rmin should be set to zero by connecting the r min pin to the v ref pin. for example, the circuit in figure 1 produces a dimming ratio of 100:1 at 1ma of lamp current, but sets the minimum ccfl current to zero (r min is connected to v ref ). in this case, the prog voltage must be kept above 1.12v to limit the ccfl current to 1ma (1ma is only a typical minimum lamp current used for illustration, con- sult lamp specifications for actual minimum allowable value) during normal operation in order to meet ccfl specifications to maximize lifetime. it should be noted that taking the prog voltage in figure 1 down to 1v (0ma ccfl current) enables dimming ratios greater than 500:1, but violates minimum ccfl current specifications in most lamps and is not recommended. alternatively, discon- necting r min from v ref and adding a 10k w resistor from r min to agnd in figure 1 sets the minimum ccfl current
lt1768 11 applicatio n s i n for m atio n wu u u per lamp to 1ma for all prog voltages but limits the dimming ratio to 6:1. trace b in figures 3a and 3b shows figure 1s ccfl current waveform operating at 1ma in pwm mode. maximum current mode (v prog > 4v) sets the vc source current to five times the current out of the 1.25v refer- enced r max pin. setting r rmax to produce ccfl current equal to the manufacturers maximum rating in this mode insures no degradation in the specified lamp lifetime. for example, setting r4 in the circuit in figure 1 to 16.2k sets the maximum ccfl current to 9ma (9ma is only a typical maximum lamp current used for illustration, consult lamp specifications for the actual value). trace a in figure 3a and 3b shows figure 1s ccfl current waveform operating at 9ma in maximum current mode. figure 3a. ccfl current for circuit in figure 1 figure 3b. ccfl current for circuit in figure 1 in linear mode (v pwm < v prog < 4v), vc source current is controlled linearly with the voltage on the prog pin. the equation for the vc source current in linear mode is i vc = (v prog C 1v)/3v (i rmax ? 5). for the best current to light conversion and highest efficiency, v pwm should be set to make the lt1768 normally operate in the linear mode. for example, in the circuit in figure 1, linear mode runs from v prog = 3v to v prog = 4v with lamp current equal to (3ma)(v prog C1v)/1v. in pwm mode (1v < v prog < v pwm ), the vc source current is modulated between the value set by minimum current mode and the value for i vc in linear mode with v prog = v pwm . the pwm frequency is equal to 22hz/c t ( m f) with its duty cycle set by the voltages on the prog and pwm pins and follows the equation: dc = [1 C (v pwm C v prog )/(v pwm C 1v)] ? 100% the lt1768s pwm mode enables wide dimming ratios while reducing the high crest factor found in pwm only dimming solutions. in the example of figure 1, pwm mode runs from v prog = 1v to v prog = 3v with ccfl current modulated between 0ma and 6ma. the pwm modulation frequency is set to 220hz by capacitor c3. when combined, these five modes of operation allow creation of a dc controlled ccfl current profile that can be tailored to each particular display. with linear mode ccfl current control over the most widely used current range, and pwm mode at the low end, the lt1768 enables wide dimming ratios while maximizing ccfl lifetimes. lamp feedback current in a typical application, the dio1/2 pins are connected to the low voltage side of the lamps. each dio pin is the common connection between the cathode and anode of two internal diodes (see block diagram). the remaining terminals of the diodes are connected to pgnd. bidirec- tional lamp current flows into the dio1/2 pins and their diodes conduct alternately on the half cycles. the diode that conducts on the negative cycle has a percentage of its current diverted into the vc pin. this current nulls against the vc source current specified by the multimode dim- ming section. a single capacitor on the vc pin provides both stable loop compensation and an averaging function to the halfwave-rectified lamp current. therefore, current into the vc pin from the lamp current programming section relates to average lamp current. the overall gain from the resistor current to average lamp current is equal to the gain from the multimode dimming block divided by the gain from the dio pin to the vc pin, trace a v prog = 4.5v i lamp = 9ma rms trace b v prog = 1.125v i lamp = 1ma rms 1ms/div trace a v prog = 4.5v i lamp = 9ma rms trace b v prog = 1.125v i lamp = 1ma rms 100 m s/div
lt1768 12 applicatio n s i n for m atio n wu u u and is dependant on the operating mode. for dual lamp displays, the transfer function for minimum current mode (i dio /i rmin ) is equal to 10a/a, and for maximum current mode (i dio /i rmax ) is equal to 100a/a. the transfer functions discussed above are between r max and r min current and average lamp current not rms lamp current. due to the differences between the average and rms functions, the actual overall transfer function be- tween actual lamp current and r min /r max current must be empirically determined, and is dependant on the particular lamp/display housing combination used. for example, in the circuit of figure 1 setting r rmin to 10k w and r rmax to 16.8 w , sets the minimum and maximum rms lamp currents for the example display to 1ma and 9ma per lamp respectively. figure 4 shows the lamp current vs program- ming voltage for the circuit in figure 1. r rmin adjusted to produce the specified current. if a wide dimming range is desired, v prog should be set to 0.75v and r rmin adjusted to produce the required dimming ratio. care must be taken when adjusting r rmin to pro- duce extreme dimming ratios. the minimum lamp current set by r rmin must be able to fully illuminate the lamp or thermometering (uneven illumination) will occur. if the desired dimming ratio cant be achieved by adjusting r rmin , the minimum lamp current can be set to zero by connecting the r min pin to the v ref pin. if the minimum current is set to less than the open lamp threshold current (approximately 125 m a), the fault pin will be activated for prog voltages between 0.5v and 1v. the values chosen for r rmax and r rmin are extremely critical in determining the lifetime of the display. it is imperative that proper measurement techniques, such as those cited in the references, be used when determining r rmax and r rmin values. lamp fault modes and single lamp operation the dio pin diodes that conduct on the positive cycle are used to detect open lamp fault conditions. if the current in either of the dio pins on the positive half cycle is less than 125 m a due to either an open lamp or lamp lowside short to ground, for a minimum of 1 pwm cycle, then the fault pin will be activated and the lamp programming current into the vc pin in high level pwm mode, linear mode, and maximum current mode, will be reduced by approximately 50%. halving the vc source current will cut the total lamp current to approximately one half of its programmed value. this function insures that the maxi- mum lamp current level set by r rmax will not be exceeded even under fault conditions. if the current in both of the dio pins on the positive cycle is less than 125 m a, and the vc pin hits its clamp value (indicating an open lamp or lamp lowside short to ground fault condition) for a mini- mum of 1 pwm cycle, the gate drive will be latched off. the latch can be cleared by setting the prog voltage to zero or placing the lt1768 in shutdown mode. since open lamp fault conditions produce high voltage ac waveforms, it is imperative that proper layout spacings between the high voltage and dio lines be observed. coupling capacitance as low as 0.5pf between the high figure 4. lamp current vs prog voltage for the circuit in figure 1 choosing r rmax and r rmin and v pwm the value for r rmax should be determined by setting v prog to 4.5v then adjusting r rmax to produce the maximum allowable current specified by the lamp manu- facturer. the voltage for the pwm pin should then be set so that the lt1768 normally operates in linear mode. a typical value for v pwm is approximately 2.5v, which limits the pwm region to 50% of the v prog input voltage range. the value for r rmin should be chosen to either produce the minimum manufacturer specified lamp current or enable a wide dimming range. if a minimum specified current is desired, the v prog should be set to 0.75v and v prog (v) 1.0 0.5 5.0 4.0 3v ( v pwm) min current pwm (freq = 220hz) max current linear 0% 100% off 9ma 6ma 0ma i ccfl (ma) 1768 f04
lt1768 13 applicatio n s i n for m atio n wu u u voltage and dio lines can cause enough current flow to fool the open lamp detection. in situations where coupling cant be avoided, resistors can be added from the dio pins to ground to increase the open lamp threshold. when resistors from the dio pins to ground are added, the values for r rmax and r rmin may need to be increased from their nominal values to compensate for the additional current. for single lamp operation, the lowside of the lamp should be connected to both dio pins, and the values of r rmax and r rmin increased to two times the values that would be used in a dual lamp configuration. in single lamp mode all fault detection will operate as in the dual lamp configura- tion, but the open lamp threshold will double. if the increase in the open lamp threshold is not acceptable, a positive offset current can be added to reduce the open lamp threshold by placing a resistor between the ref and dio pins (a 33k resistor will reduce the open lamp thresh- old by approximately 100 m a ((v ref C v dio + )/33k). when an offset current is added, the values for r rmax and r rmin may need to be increased from their nominal values to compensate for the offset current. vc compensation as previously mentioned a single capacitor on the vc pin combines the error signal conversion, lamp current aver- aging and frequency compensation. careful consideration should be given to the value of capacitance used. a large value (1 m f) will give excellent stability at high lamp cur- rents but will result in degraded line regulation in pwm mode. on the other hand , a small value (10nf) will give excellent pwm response but might result in overshoot and poor load regulation. the value chosen will depend on the maximum load current and dimming range. after these parameters are decided upon, the value of the vc capacitor should be increased until the line regulation becomes unacceptable. a typical value for the vc capacitor is 0.033 m f. for further information on compensation please refer to the references or consult the factory. current sense comparator the lt1768 is a current mode pwm controller. under normal operating conditions the gate is driven high at the start of every oscillator cycle. the gate is driven back low when the current reaches a threshold level proportional to the voltage on the vc pin. the gate then remains low until the start of the next oscillator cycle. the peak current is thus proportional to the vc voltage and controlled on a cycle by cycle basis. the peak switch current is normally sensed by placing a sense resistor in the source lead of the output mosfet. this resistor converts the switch current to a voltage that can be compared to a fraction of the vc voltage [(v vc C v diode )/30] . for normal conditions and a gate duty cycle below 50%, the switch current limit will correspond to i pk = 0.1/r sense . for gate duty cycles above 50% the switch current limit will be reduced to approximately 90mv at 80% duty cycle to avoid subharmonic oscillations associated with current mode controllers. when the lamp current is programmed to pwm mode, the vc pin will slew between voltages that represent the minimum and maximum pwm lamp currents. the slew time affects the line regulation at low duty cycle, and should be kept low by making the sense resistor as small as possible. the lowest value of sense resistor is deter- mined by switching transients and other noise due to layout configurations. a good rule of thumb is to set the sense resistor so that the voltage on the vc pin equals 2.5v when the pwm current is in maximum mode (v prog = v pwm ). typical values of the sense resistor run in the 25m w to 50m w range for large displays, and can be implemented with a copper trace on the pcb. since the maximum threshold at the sense pin is only 100mv, switching transients and other noise can prema- turely trip the comparator. the lt1768 has a blanking period of 100ns which prohibits premature switch turn off, but further filtering the sense resistor voltage is recommended. a simple rc filter is adequate for most applications. (figure 5.) figure 5. sense pin filter sense gate lt1768 100 w 2.2nf 0.025m w 1768?f05
lt1768 14 up current source. the lt1768 thermal shutdown tem- perature is set at 160 c. a buffered version of the internal 5v is present at the v ref pin and is capable of supplying up to 10ma of current. note that using any substantial amount of current from the v ref pin will increase power dissipation in the device, which will reduce the useful operating ambient temperature range. supply and input voltage sequencing for most applications, where the shdn pin is left floating, and the voltages on the pwm and prog pins are derived from the v ref pin, the lt1768 will power-up and power- down correctly when the voltage to the v in pin is applied and removed. in applications where the voltage inputs for the v in pin, shdn pin, pwm pin, and the prog pin originate from different sources (power supply, micropro- cessors etc.), care must be taken during power up/down sequences. for proper operation during the power-up sequence, the voltage on the following pins must be taken from zero to their appropriate values in the following order; v in pin, shdn pin, pwm pin and prog pin. for proper operation during the power-down sequence, the order must be reversed. for example, in the circuit of figure 1 where the shdn pin is left floating, and the pwm pin voltage is derived from a resistor divider to the v ref pin, the proper power-up sequence would be to take the v in pin from zero to its value then apply either a voltage or pwm signal to the prog pin. the power-down sequence for the circuit in figure 1 would be to take the prog pin voltage to zero, then take the v in pin voltage to zero.if the prog voltage in the circuit of figure 1 is present before the v in supply voltage, proper power supply sequecing can be achieved by implementing the circuit shown in figure 7. applicatio n s i n for m atio n wu u u 1768 ?g06 pgnd gate bat 85 lt1768 gate the lt1768 has a single high current totem pole output stage. this output stage is capable of driving up to 1.5a of output current. cross-conduction current spikes in the totem pole output have been eliminated. the gate pin is intended to drive an n-channel mosfet switch. rise and fall times are typically 50ns with a 3000pf load. a clamp is built into the device to prevent the gate pin from rising above 13v in order to protect the gate of the mosfet switch. the gate pin connects directly to the emitter of the upper npn drive transistor and the collector of the lower npn drive transistor in the totem pole. the collector of the lower transistor, which is n-type silicon, forms a p-n junction with the substrate of the device. this junction is reversed biased during normal operation. in some applications the parasitic lc of the external mosfet gate can ring and pull the gate pin below ground. if the gate pin is pulled negative by more than a diode drop the parasitic diode formed by the collector of the gate npn and the substrate will turn on. this can cause erratic operation of the device. in these cases a schottky clamp diode is recommended from the gate pin to ground. (figure 6.) figure 6. schottky gate clamp 49.9k 10k 10 f 0 to 5v or 1khz pwm vn2222ll 1768 f07 v in prog lt1768 figure 7. circuit insures proper supply sequencing when dimming voltage exists before main power supply reference the internal reference of the lt1768 is a trimmed bandgap reference. the reference is used to power the majority of the lt1768 internal circuitry. the reference is inactive if the lt1768 is in undervoltage lockout, shutdown mode, or thermal shutdown. the undervoltage lockout is active when v in is below 7.9v and the lt1768 is in shutdown mode when the voltage on the shdn pin is pulled below 1v. the shdn pin has 200mv of hysteresis and a 7 m a pull-
lt1768 15 applicatio n s i n for m atio n wu u u together with minimum trace between them. if space constraints prohibit the transformer t1 placement next to c1, local bypassing (c2) for the center tap of transformer t1 should be used. special attention is also required for the layout of the high voltage section to avoid any unpleasant surprises. please refer to the references for an extensive discussion on high voltage layout techniques. applications support linear technology invests an enormous amount of time, resources, and technical expertise in understanding, de- signing and evaluating backlight solutions for systems designers. the design of an efficient and compact back- light system is a study of compromise in a transduced electronic system. every aspect of the design is interre- lated and any design change requires complete re-evalu- ation for all other critical design parameters. linear technology has engineered one of the most complete test and evaluation setups for backlight designs and under- stands the issues and trade-offs in achieving a compact, efficient and economical customer solution. linear tech- nology welcomes the opportunity to discuss, design, evaluate, and optimize any backlight system with a cus- tomer. for further information on backlight designs, con- sult the references below. references 1. williams, jim. november 1995. a fourth generation of lcd backlight technology. linear technology corpora- tion, application note 65. 1768 f08 c1 d1 l1 t1 v in c2 *optional bold lines indicate high current paths lt1768 gate pgnd v in sense figure 8 supply bypass and layout considerations proper supply bypassing and layout techniques must be used to insure proper regulation, avoid display flicker, and insure long term reliability. figure 8 shows the applications critical high current paths in thick lines. ideally, all components in the high current path should be placed as close as possible and connected with short thick traces. the most critical consideration is that t1s center tap, the schottky diode d1, lt1768s v in pin, and a low esr capacitor (c1) be connected directly
lt1768 16 lt1768 v ref prog agnd 1768 ta05 r1 49.9k c1 10 m f 0 ?>5v 1khz pwm dc intensity control pwm intensity control 1768 ta04 lt1768 v ref prog agnd r1 100k pot typical applicatio n s u lt1768 v ref prog agnd 1768 ta06 r1 49.9k r id r1 10k c1 10 m f 0 ?>3.3v or 0 ?>5v 1khz pwm q1 vn2222ll pwm intensity control from 3.3v or 5v logic
lt1768 17 1768 ta08 ltc1663 scl sda gnd v cc v out lt1768 v ref prog agnd 2-wire serial interface intensity control typical applicatio n s u lt1768 v ref prog agnd 1768 ta07 r1 49.9k r1 50k c1 10 m f ltc1426 clk1 shdn clk2 pwm2 pwm1 agnd s1 s2 v cc v ref pushbutton intensity control
lt1768 18 typical applicatio n s u 24 watt four lamp ccfl supply 1768 ta10 c8, 0.22 m f ctx110607 r6 499 r9 0.0125 q1a zdt1048 q1b zdt1048 l2 22m h l1 22m h t1 c12, 22pf x1 r7 499 c5 0.1 m f c1 33 m f q2 si3456dv d2 mbrs130lt3 lamp d4 bat54 r3 69.8k r1 49.9k r2 30.1k r5 125k r11 1k r4 11.3k c3 0.1 m f c4 10 m f c2 0.047 m f v in = 12v prog 0v to 5v or 1khz pwm c6 1 m f lt1768 di02 pgnd gate v c agnd c t prog di01 sense shdn r min r max pwm fault shutdown fault v ref v in 5v 15 16 1 12 11 10 9 14 13 5 6 7 8 4 3 2 c13, 22pf x2 lamp c14, 22pf x3 lamp c15, 22pf x4 lamp c7 2200pf r8 100 c9, 0.22 m f ctx110607 t2 c10, 0.22 m f ctx110607 t3 c11, 0.22 m f ctx110607 t4 d3 bat54 r10 1k
lt1768 19 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.009 (0.229) ref gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
lt1768 20 part number description comments lt1170 current mode switching regulator 5.0a, 100khz lt1182/lt1183 ccfl/lcd contrast switching regulators 3v v in 30v, ccfl switch: 1.25a, lcd switch: 625ma, open lamp protection, positive or negative contrast lt1184 ccfl current mode switching regulator 1.25a, 200khz lt1186 ccfl current mode switching regulator 1.25a, 100khz, smbus interface lt1372 500khz, 1.5a switching regulator small 4.7 m h inductor, only 0.5 square inch of pcb lt1373 250khz, 1.5a switching regulator 1ma i q at 250khz, regulates positive or negative outputs lt1786f smbus controlled ccfl switching regulator precision 100 m a full scale current dac linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2000 sn1768 1768fs lt/tp 0901 2k ? printed in usa related parts typical applicatio n u 4 watt single lamp ccfl supply 1768 ta09 c7 0.33 m f r7 499 r6 0.05 q1a zdt1048 q1b zdt1048 l1 33 m h t1 ctx110607 c9 33pf x1 c5 0.1 m f c1 33 m f q2 si3456dv d2 mbrs130lt3 lamp r3 61.9k r1 49.9k r2 39.2k r5 124k r4 31.6k c3 0.22 m f c4 10 m f c2 0.047 m f v in = 9v to 24v prog 0v to 5v or 1khz pwm c6 1 m f lt1768 di02 pgnd gate v c agnd c t prog di01 sense shdn r min r max pwm fault shutdown fault v ref v in 5v 15 16 1 12 11 10 9 14 13 5 6 7 8 4 3 2 c8 1000pf r2 100

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